1. Field of the Invention
The present invention relates to semiconductor memory devices and fabrication methods therefor. More particularly, the invention relates to semiconductor memory devices having MOS field effect transistors (FETs) of a planar cell structure, and to fabrication methods therefor.
2. Description of the Related Arts
For higher-level integration of a semiconductor memory device of the type which includes MOS FETs formed in a memory cell portion and peripheral circuitry portion thereof, a construction shown in FIG. 1 has been proposed.
To fabricate such a semiconductor memory device, a plurality of source/drain regions 2a each serving as a bit line are formed in a generally parallel relation in a memory cell portion M of a semiconductor substrate 1.
In turn, gate electrodes 3a each serving as a word line and extending perpendicular to the source/drain regions 2a are formed on the source/drain regions 2a with intervention of a gate insulation film (not shown) and, at the same time, a gate electrode 3b of MOS FETs is formed in a peripheral circuitry portion C.
Subsequently, source/drain regions 2b of the MOS FETs are formed in the peripheral circuitry portion C by way of ion implantation using the gate electrode 3b as a mask.
Device isolation is achieved by implanting into the memory cell portion M an impurity of a conductivity type opposite to that of an impurity contained in the source/drain regions 2a with the use of the gate electrodes 3a as a mask. Threshold voltages (Vth) of channels of the transistors formed in the memory cell portion M and the peripheral circuitry portion C are controlled by ion implantation over the entire surface of the substrate.
Such a semiconductor memory device, in general, suffers from deterioration in the characteristics of the MOS FETs, e.g., variation in the threshold voltage Vth, distortion of a V-I saturation characteristic curve and reduction in the operation speed, which may be caused due to a so-called short channel effect when the channel length is reduced for micro-fabrication of the MOS FETs in the peripheral circuitry portion.
To cope with this problem, a drain engineering technique is employed to suppress the short channel effect of the MOS FETs in the peripheral circuitry portion C. More specifically, a shallow LDD (lightly doped drain) region is formed to reduce expanse of an electric field from the drain region to a channel region and, in a step subsequent to the formation of the gate electrode, impurity ions of a conductivity type opposite to that of the impurity contained in the source/drain regions are implanted into a region adjacent to the shallow LDD region in self-alignment with the gate electrode.
In another method, a shallow LDD region is formed like the aforesaid method, and the impurity concentration around the surface of the channel region is set higher, while expanse of the electric field from the drain region to the channel region is reduced.
In the process for forming the MOS FETs in the memory cell portion of the planar cell structure, however, the formation of the source/drain regions thereof is carried out in a step precedent to the formation of the gate insulation film, followed by the formation of the gate electrode thereof and the formation of the source/drain regions of the MOS FETs in the peripheral circuitry portion. Accordingly, it is difficult to allow the source/drain regions in the memory cell portion to have a reduced depth. Thus, the source/drain regions in the memory cell portion each have a greater depth than the source/drain regions of the MOS FETs in the peripheral circuitry portion, so that a variation in the potential of a deeper portion of a channel of each transistor in the memory cell portion cannot be suppressed which is caused due to upward expanse of an electric field generated around a drain of the transistor. Hence, the short channel effect cannot be suppressed.
In the MOS FET of the memory cell portion of the planar cell structure, the source/drain regions thereof overlap the gate electrode, so that impurity ions of a conductivity type opposite to that of the impurity contained in the source/drain regions cannot be implanted in a region adjacent to the LDD region in self-alignment with the gate electrode, unlike the aforesaid drain engineering technique. This makes it impossible to achieve higher-level integration of memory cells.
An exemplary method considered to be effective for suppressing the short channel effect of the MOS FETs in the memory cell portion of the planar cell structure is to increase the threshold voltage Vth by increasing the impurity concentration in the channels thereof. In a presently available semiconductor fabrication process, however, the threshold voltages Vth of the channel regions of the transistors in the memory cell portion and the peripheral circuitry portion are controlled by ion implantation over the entire surface of the semiconductor substrate. Therefore, it is difficult to control only the threshold voltages of the MOS FETs in the memory cell portion (see FIGS. 13 and 14). Further, since the MOS FETs in the peripheral circuitry portion should be operated at a relatively high speed in the semiconductor device, it is not preferable to increase the threshold voltages Vth thereof. More specifically, an extremely high threshold voltage Vth results in a reduced current flowing through the transistors in the peripheral circuitry portion. Further, it is disadvantageous that it takes a long time before the transistors are turned on when current is supplied to the gate electrode of the transistors.
In accordance with a conventional technique related to the semiconductor memory device of the so-called planar cell structure, the integration level of the semiconductor memory device cannot be increased by suppressing the short channel effect of the transistors in the memory cell portion while allowing the transistors in the peripheral circuitry portion to operate at a relatively high speed. Therefore, it is currently impossible to achieve the higher-speed operation and higher-level integration of the semiconductor memory device of the planar cell structure.